Mathematik | Informatik
Rufus Spyra, 2007 | Herrenschwanden, BE
This paper presents the design and implementation of an 8-bit computer architecture in SystemVerilog, following the principles of chip design while leveraging modern open-source development tools. The project completes all key stages of chip development, from high-level requirements engineering to logic design, verification, and synthesis using the TinyTapeout open-source ASIC workflow. Automated testing is used to validate functionality at both register-transfer level and gate level. The final design is synthesized and submitted for production in silicon with the TinyTapeout project. The chip is expected in the first quarter of 2026. This project serves as an illustration of the capabilities of current open-source tooling and illustrates the feasibility of open and collaborative silicon design and production.
Introduction
The goal of this project is to develop an 8-bit computer architecture that follows real-world chip design processes and can be produced as an application-specifc integrated circuit in silicon. The architecture is designed to be as simple as possible while adhering to the Von Neumann Architecture while using exclusively open-source tools.
Methods
The development process was carried out using SystemVerilog with the TinyTapeout workflow. The architecture was divided into individual modules (ALU, registers, memory, control unit), which were incrementally designed, implemented, integrated and tested. Verification was conducted using automated testbenches with Cocotb at both the RTL and gate levels. After successful simulation, the design was prepared for production with the TinyTapeout toolchain by synthesizing with YoSys and hardening with OpenROAD and additional tools. The final version was submitted for fabrication, with fabricated chips expected in 2026.
Results
The implemented 8-bit architecture meets all defined requirements: It operates on an 8-bit data bus, follows the Von Neumann Architecture, and is Turing-equivalent. Automated tests successfully validated all modules. The synthesis and hardening processes demonstrated a stable and reproducible design flow. The final design occupied 61% of two tiles allowing efficient routing to meet the timing constraints.
Discussion
The architecture achieves its intended objectives. The TinyTapeout workflow proved suitable for this project, despite limitations in the ability to modify the backend processes. The implementation of a Brainfuck interpreter confirmed the system’s Turing equivalence.
Conclusions
This project demonstrates that it is possible to design and fabricate a functional computer architecture using open-source tools. The next steps include testing the fabricated chips to verify the design’s correctness and non-functional characteristics in silicon. Additional tools will be created to ease the development of programs for this architecture.
Würdigung durch den Experten
Dr. David Perels
Einen ASIC zu entwickeln, zu verifizieren und ein Tapeout durchzuführen, ist normalerweise Aufgabe von Entwicklungsteams einer F&E-Abteilung, oder? Rufus Spyras Projekt hatte jedoch genau dieses Ziel: Ein 8-Bit-Prozessor wurde von Grund auf entwickelt und verifiziert. Beeindruckend war, mit welcher Energie und welchem Ideenreichtum er dies anging, wobei viele industrienahe Methoden genutzt wurden. Er konnte eine gründliche Dokumentation verfassen, um den produzierten ASIC später auf dem Evaluation Board problemlos in Betrieb zu nehmen.
Prädikat:
hervorragend
Sonderpreis «Regeneron International Science and Engineering Fair (ISEF)» gestiftet von der Gebauer Stiftung
Gymnasium Kirchenfeld, Bern
Lehrer: Stefan Rothe